Dynamic Partial based Single Event Upset (SEU) Injection Platform on FPGA
نویسندگان
چکیده
SRAM based FPGAs are attracting considerable interest especially in aerospace applications due to their high reconfigurability, low cost and availability. However, these devices are strongly susceptible to space radiation effects which are able to cause unwanted single event upsets (SEUs) in the configuration memory. In order to mitigate the SEU effects, various methods have been investigated in literatures. Fault injection methods are required to evaluate the efficiency of the hardening techniques. This paper has proposed a dynamic partial reconfiguration based fault-injection platform (DPR-FIP) for emulating the SEU faults in FPGA configuration memory. Besides the SEU faults, DPRFIP tool supports cumulative SEU, multi-event upset, and single event transient faults in combinational parts and flip-flops. General Terms Reliability, Digital Circuits, Fault Tolerant Design, Testing.
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